High-bandwidth transmission of data in on-chip and multi-chip module settings requires robust, energy-efficient signaling techniques. While conventional single-ended transmission techniques are suitable for short-distance data transmission, these techniques can suffer significant signal degradation due to cross-talk in longer-distance, high-density configurations needed for global fly-over and inter-chip data transmission. In certain high-speed, high-density parallel interconnect configurations, cross-talk among parallel data channels may limit the practical transmission distance to a few millimeters, which is generally inadequate for global fly-over and inter-chip transmission.
One technique for mitigating cross-talk is fully-differential signaling, with twisted channel pairs. However, this technique is relatively expensive as it requires twice as many signal wires per channel, and consequently may suffer reduced bandwidth density and energy efficiency compared to single-ended signaling. Another technique for mitigating cross-talk involves adding in-line analog compensation circuits to the receiver and/or transmitter end of a parallel signal channel. The analog compensation circuits implement a multiple-input, multiple-output equalizer having an appropriate frequency-domain matrix to compensate for channel response. However, this approach consumes significant power and requires additional die area and complexity to accommodate the analog compensation circuits. Thus, there is a need for addressing these issues and/or other issues associated with the prior art.